A dynamic random access memory (DRAM) device includes an array of memory cells wherein each memory cell includes a memory cell access transistor and a memory cell (information storage) capacitor. In general, a memory cell capacitor requires a storage capacitance of at least about 30 fF to reduce soft errors which may result from .alpha.-particles. As the integration densities of DRAMs increase, however, reduced space is available for each memory cell capacitor.
As will be understood by those having skill in the art, the capacitance of a memory cell capacitor can be determined using the following formula: EQU C=.epsilon..sub.0 .epsilon.A/d
In particular, C represents the storage capacitance for the capacitor, .epsilon..sub.0 represents the dielectric constant in a vacuum, .epsilon. represents the dielectric constant of the capacitor dielectric layer, A represents the effective area of the capacitor, and d represents the thickness of the dielectric layer. Accordingly, a memory cell capacitance can be increased by increasing a dielectric constant for the dielectric layer, by increasing an effective area for the capacitor, and by decreasing a thickness of the dielectric layer.
Reductions in the thickness of the dielectric layer may be limited when fabricating highly integrated memory devices. In particular, when a dielectric layer such as an NO layer or a Ta.sub.2 O.sub.5 layer having a thickness of less than approximately 100 Angstroms is used, the reliability of the dielectric layer may be reduced as a result of Fowler-Nordheim currents.
Three-dimensional capacitor structures have been developed to increase the effective area of memory cell capacitors. The steps used to fabricate these three-dimensional structures, however, may be complicated and costly. For example, three-dimensional structures developed for memory cell capacitors include the stack type capacitor structure, the trench type capacitor structure, the fin type capacitor structure, and the cylinder type capacitor structure. These structures have been used for 4 MB and 16 MB DRAMs, but these capacitor structures may not be suitable for use in 64 MB and 256 MB DRAMs. In particular, the scaling down of trench type capacitor structures may result in leakage current between trenches. Moreover, stack type capacitor structures, fin type capacitor structures, and cylinder type capacitor structures may result in severely uneven surfaces when providing relatively high storage capacitances. These uneven surfaces may adversely affect subsequent photolithography and etch steps.
Dielectric layers for memory cell capacitors have been produced using materials having dielectric constants that are high relative to the dielectric constant of a NO dielectric layer. For example, Y.sub.2 O.sub.3, Ta.sub.2 O.sub.5, TiO.sub.2 have been used to provide dielectric layers for memory cell capacitors. In addition, ferroelectric materials such as PZT(Pb(Zr, Ti)O.sub.3), and BST(BaSrTi) have also been used. Ferroelectric materials have spontaneous polarizations, and ferroelectric materials can have a dielectric constant in the range of 100 to 1,000. Accordingly, when such a ferroelectric material is used to create a dielectric layer for a memory cell capacitor having a predetermined effective area, the dielectric layer can have a thickness of several hundreds of Angstroms while providing the same capacitance as a memory cell capacitor with the same predetermined effective area having a dielectric oxide layer with a thickness of less than 10 Angstroms.
In particular, BST can retain a relatively high dielectric constant at a relatively high frequency when compared to PZT. In addition, BST can be changed to a normal dielectric substance according to the ratio Bs/Sr thereby reducing fatigue and aging. BST has thus been used to provide the dielectric layer for memory cell capacitors.
Ferroelectric layers can be formed on semiconductor devices using sputtering steps, metal-organic chemical vapor deposition (MOCVD) steps, spin coating steps, and aerosol steps as well as other deposition steps known to those having skill in the art. Moreover, BST layers can be formed using these and other steps. In particular, sputtering steps may be preferred when depositing ferroelectric layers because of its repeatability and relative simplicity. Because a dielectric layer of BST is preferably not deposited directly on a polysilicon electrode, however, improved electrodes may be required when fabricating a DRAM memory cell capacitor including a BST dielectric layer. In particular, when a BST layer is sputtered on a polysilicon electrode, the surface of the polysilicon electrode may be partially oxidized in an oxygen ambient, and a SiO.sub.2 layer may be formed thereon. This oxide layer may thus reduce the dielectric constant of the BST layer thereby reducing the capacitance for the memory cell capacitor.
Accordingly, the memory cell capacitor electrode may include a conductive plug, a diffusion barrier layer, and a platinum layer instead of a polysilicon electrode. Accordingly, the BST dielectric layer can be formed reducing the disadvantages associated with the oxidation of the polycrystalline capacitor electrode.
Sputter deposited BST layers, however, may have poor step coverage, and it may thus be difficult to deposit a BST layer on the lateral surfaces of the capacitor electrode. Accordingly, memory cell capacitors including BST dielectric layers may be prone to leakage currents in excess of 100nA/cm.sup.2 flowing through the portions of the BST layer deposited on the lateral surfaces of the capacitor electrode. Moreover, sputtering steps used to deposit BST layers may be carried out at relatively high temperatures. Accordingly, oxygen may diffuse through the lateral surfaces of the capacitor electrode including the conductive plug, the diffusion barrier layer, and the platinum layer. The diffusion barrier layer may thus be oxidized thus making it difficult to fabricate a capacitor including a BST dielectric layer.
Techniques for protecting the metal barrier layer have thus been developed wherein the lateral surfaces of the capacitor electrode are enclosed by a SiO.sub.2 layer or by another insulating layer such as Si.sub.3 N.sub.4. In particular, a method for protecting the metal barrier layer will now be discussed with reference to FIGS. 1A to 1E. As shown in FIG. 1A, an insulating layer 12 is formed on a semiconductor substrate 10. A photoresist mask exposes portions of the insulating layer 12 which are then etched to form contact holes through the insulating layer 12 exposing portions of the substrate 10.
The photoresist mask is then removed, and exposed portions of the substrate 10 are covered with a first conductive layer 14a as shown in FIG. 1B. In particular, the conductive layer 14a is formed on exposed portions of the substrate 10 and on the insulating layer 12 opposite the substrate 10. The first conductive layer 14a can be a layer of polycrystalline silicon (polysilicon).
The first conductive layer 14a is then etched back to provide the conductive plugs 14b in the contact holes through the insulating layer 12, as shown in FIG. 1C. A diffusion barrier layer 16 is then deposited on the conductive plugs 14b and on the insulating layer 12 as shown in
FIG. 1D. A second conductive layer 18 is then deposited on the diffusion barrier layer 16, and the second conductive layer 18 can be a layer of platinum (Pt). A photoresist mask is then formed on the second conductive layer 18, and this photoresist mask is used to pattern the diffusion barrier layer 16 and the second conductive layer 18 to provide a capacitor electrode (storage node electrode), as shown in FIG. 1E. The photoresist mask is then removed. Accordingly, the first capacitor electrode 19 includes the conductive plugs 14b, the diffusion barrier layer 16, and the Pt layer 18.
A second insulating layer such as a layer of SiO.sub.2 or Si.sub.3 N.sub.4 is then deposited on the insulating layer 12 and on the capacitor electrode 19 to reduce oxidation of the diffusion barrier layer 16. The insulating layer is then subjected to an anisotropic dry etching step or a chemical mechanical polishing (CMP) step so that lateral spacers 20 of an insulating material are formed on the lateral surfaces of the capacitor electrode 19. Accordingly, the lateral surfaces of the capacitor electrode are passivated by the spacers 20. The metal barrier layer 16 can thus be protected from an oxidation during the subsequent sputter deposition of the BST layer.
A BST layer is then sputter deposited on the capacitor electrode 19, on the insulating layer 12, and on the lateral spacers 20. A third conductive layer is then deposited on the BST layer opposite the capacitor electrode 19 to provide a second capacitor electrode (plate node electrode) thereby providing a memory cell capacitor for a DRAM. In particular, a Pt layer can be used to provide the third conductive layer. The fabrication of the lateral spacers, however, may increase the complexity and cost of the manufacturer of a memory device including the capacitor discussed above.
Another method for protecting a diffusion barrier layer while forming a capacitor electrode includes the following steps. An insulating layer is formed on the semiconductor substrate, and contact holes are formed in the insulating layer exposing portions of the semiconductor substrate. The diffusion barrier layer is formed on the exposed surface portions of the substrate in the contact holes. A platinum electrode layer is then deposited on the surface of the diffusion barrier layer in the contact holes and on the surface of the insulating layer. Accordingly, the oxygen diffusion distance into the top and lateral surfaces of the Pt layer is increased, and it is thus possible to protect the diffusion barrier layer from oxidation. The Pt layer can be formed using a chemical vapor deposition step, or by a reflowing step carried out by a predetermined temperature after deposition of the Pt layer.
Chemical vapor deposition steps, however, are not generally used to form Pt layers when forming capacitors for semiconductor devices using mass production techniques. Furthermore, Pt electrodes formed by chemical vapor deposition may have relatively low purity and poor surface characteristics. The properties of capacitors including Pt layers formed by chemical vapor deposition may thus be relatively poor thereby reducing the performance of semiconductor devices including these capacitors. Accordingly, there continues to exist a need in the art for improved methods for forming capacitor electrodes.